1. Field of the Invention
The present invention relates to a semiconductor device and a data storage apparatus, which include a data transfer circuit which can be used in a semiconductor element configured to have a cell array structure like a flash memory and an image sensor in which a large volume of data is read or written sequentially at high speed.
2. Description of the Related Art
In a flash memory nowadays, units for read and write operations are as great as 16 Kbit, and it takes time to some extent for an operation to read data out of an array and to transfer the data to an input/output circuit of a chip.
FIG. 1 shows a diagram depicting an exemplary configuration of a circuit system to transfer data from a cell array to an input/output circuit in a typical flash memory (semiconductor device).
A flash memory 1 shown in FIG. 1 has a cell array 2, a sense amplifier group 3, a page buffer 4 configured to have latches arranged in parallel, a column switch group 5, a sense amplifier 6, and an input/output circuit 7.
In the case of the flash memory, as shown in FIG. 1, data transfer from the cell array 2 to the input/output circuit 7 on a chip was conducted in such a way that switches SW for the number of necessary items of data are simply connected to data lines DL and the potential on the data lines DL is sensed. For example, when the page size is 512 bytes that is the unit of reading data in the flash memory, 512 transistors are connected to a single data line DL, signals corresponding to data logic 0/1 are outputted to the data line DL, and the signals are amplified by the sense amplifier 6 on the input/output circuit for data transfer.
In this case, generally, the length of the data line DL is as long as a few mm, and a large number of transistors as many as 512 transistors is connected. Therefore, the delay time of the data line becomes a bottleneck, causing difficulties of high speed data transfer. At the product level, the cycle time is about 25 ns.
In addition, nowadays, page size is increased from 512 bytes to 2 K bytes and further to 4 K bytes, the delay time on the data line DL becomes a greater problem.
In order to transfer data at high speed in this basic structure, such a scheme is known that data lines are provided in two system lines and the two groups of data lines are operated alternately. However, in this scheme, the cycle time can be reduced by half, but this does not make a drastic solution.
On the other hand, when data in the array structure is read sequentially, such a scheme is known that data is temporarily held on registers serially connected and clocks are supplied to the registers to transfer data sequentially as shift registers do (for example, see JP-A-6-290585 (Patent Reference 1)).
In this scheme, since the cycle time for data transfer is basically decided by the delay time for a single register, significantly high speed data transfer is made possible.